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Digital logic (gates / K-map / truth table)

Native digital-logic engine — three modes in one. `type gates` for IEC-style gate schematics (AND, OR, NOT, NAND, NOR, XOR, XNOR, BUF), `type kmap` for 2-4 variable Karnaugh maps with Gray-coded rows / columns and highlighted 1-cells, `type truthtable` for full truth tables with output-coloured cells. Covers the EE / CS undergraduate digital-logic curriculum.

Templates
65
Source language
plaintext
Workstation
Studio
Engine id
logic
Open in Studio

In the same space

Most users come to Digital logic (gates / K-map / truth table) from Logisim sketches or Textbook digital-logic figures. Glyph runs this engine in the browser — no install, shareable via URL, exportable to PNG / SVG / PDF / source.

Syntax at a glance

type gates
input A at (0,0)
gate AND G1 at (3,0)
output Y at (6,0)
wire A G1
wire G1 Y

Paste this in the Studio code pane to see Digital logic (gates / K-map / truth table) render live. The full grammar is at the upstream-docs link above.

Sample templates

All 65 →
chem
Logic — half adder

Two-input half adder with XOR (sum) and AND (carry).

chem
Logic — SR latch (NAND)

Cross-coupled NAND SR latch.

chem
Logic — Karnaugh map (XOR)

2-variable K-map for the XOR function.

chem
Logic — Karnaugh map (3-input majority)

Majority function K-map (3 variables).

math
Logic — truth table (implication)

Truth table for A implies B.

chem
Physics — Logic: full adder

One-bit full adder built from two XOR, two AND and one OR gate.

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